The present invention relates to a MOS (metal oxide semiconductor) semiconductor device and, more specifically, to a MOS integrated circuit in which a source diffusion layer and a semiconductor substrate (or a well region) are at the same potential.
In a conventional MOS integrated circuit, a source contact has to be formed on a source diffusion layer. Therefore, a MOS integrated circuit is generally designed under design rules having an inclusion relation between the source diffusion layer and source contact.
FIGS. 1A to 1C schematically show the arrangement of a CMOS (complementary MOS) circuit which is designed under conventional design rules. Of these figures, FIG. 1A is a plan view of the CMOS circuit, FIG. 1B is a cross-sectional view of the CMOS circuit taken along line 1B--1B of FIG. 1A, and FIG. 1C is a cross-sectional view of the CMOS circuit taken along line 1C--1C of FIG. 1A.
As shown, an N-type well region 102 and a P-type well region 103 are formed selectively on a P-type Si (silicon) substrate 101. An element isolation region 104 having an STI (shallow trench isolation) structure is formed selectively in a surface area of the Si substrate 101, as are an active region 105 of a P-channel MOS transistor and an active region 106 of an N-channel MOS transistor.
The top surfaces of the active regions 105 and 106 are covered with their respective gate insulation films 107. A gate polysilicon electrode 108 is provided so as to connect the active regions 105 and 106 with each other through the gate insulation films 107. The electrode 108 has side walls 109, 109 on both sides thereof.
In the active region 105 of the P-channel MOS transistor, P.sup.- -type regions 105a and 105a each having an LDD (lightly doped drain) structure are formed in a surface area of the N-type well region 102 using the gate polysilicon electrode 108 as a mask, and P.sup.+ -type diffusion layers 105b and 105b serving as source and drain regions are formed therein using the electrode 108 and side walls 109 as masks.
A source contact 110 is formed on one (source) of the P.sup.+ -type diffusion layers 105b and 105b through the corresponding gate insulation film 107. A drain contact 111 is formed on the other (drain) of the layers 105b through the corresponding gate insulation film 107.
In the active region 106 of the N-channel MOS transistor, N.sup.- -type regions 106a having the LDD structure are formed in a surface area of the P-type well region 103 using the gate polysilicon electrode 108 as a mask, and N.sup.+ -type diffusion layers 106b and 106b serving as source and drain regions are formed therein using the electrode 108 and side walls 109 as masks.
A source contact 112 is formed on one (source) of the N.sup.+ -type diffusion layers 106b and 106b through the corresponding gate insulation film 107. A drain contact 113 is formed on the other (drain) of the layers 106b and 106b through the corresponding gate insulation film 107.
In the CMOS circuit having the above arrangement, a negative or positive voltage is applied to the gate polysilicon electrode 108 to bring the P.sup.+ -type diffusion layers 105b and 105b and the N.sup.+ -type diffusion layers 106b and 106b into conduction or out of conduction. Thus, the P-channel or N-channel MOS transistor performs its switching operation.
In the above CMOS circuit, however, the P.sup.+ -type diffusion layers 105b and 105b have to be formed far away from an interface A between the N- and P-type well regions 102 and 103 in order to prevent a short circuit from being caused between the P-type well region 103 and P.sup.+ -type diffusion layers 105b and 105b. Usually, a distance B between each of the P.sup.+ -type diffusion layers 105b and 105b and the interface A is set to greater than a predetermined value (a required distance under design rules between the P-type well region and P.sup.+ -type diffusion layers) in consideration of punch through between the P-type well region 102 and P.sup.+ -type diffusion layers 105b and 105b and variations in work precision of the N- and P-type well regions 102 and 103 and P.sup.+ -type diffusion layers 105b and 105b.
Since, as described above, the source contact needs to be formed on the source diffusion layer (due to an inclusion relation therebetween), each of the P.sup.+ -type diffusion layers 105b and 105b should be formed larger than the source contact 110 in the P-channel MOS transistor.
For the above reason, as illustrated in FIG. 2, a range (a hatched area) C delimited by distances B and B' with regard to the interface A between the regions 102 and 103 is a prohibited area (a so-called dead space) where the P.sup.+ -type diffusion layers 105b and 105b cannot be formed, thereby causing a problem in which the dead space C increases the layout area and the chip size.
This problem is true of MOS integrated circuits other than the foregoing CMOS circuit, such as a MOS integrated circuit in which a substrate contact is formed separately from the source contact.
FIG. 3 is a schematic plan view illustrating a MOS integrated circuit as a flip-flop memory cell (or basic memory cell) designed under conventional design rules.
Referring to FIG. 3, in the conventional memory cell, a P-type well region (semiconductor substrate) 42 is formed so as to surround an N-type well region (semiconductor substrate) 41, and an element isolation region 43 is formed selectively in the surface areas of the N-type well region 41 and P-type well region 42, and a substantially T-shaped active region 44 of the P-channel MOS transistor and an active region 45 of the N-channel MOS transistor are arranged opposite to each other.
The top surfaces of the active regions 44 and 45 are covered with their respective gate insulation films 46. Two gate polysilicon electrodes 47a and 47b are arranged in parallel to each other to connect the active regions 44 and 45 with each other through the gate insulation films 46. The electrode 108 has side walls 109 on both sides thereof.
In the active region 44 of the P-channel MOS transistor, P.sup.+ -type drain diffusion layers 48 and 48 whose potential differs from that of the N-type well region 41 are formed in those portions of the surface of the N-type well region 41 which correspond to drain regions outside the gate polysilicon electrodes 47a and 47b. There is a fixed distance B.sub.1 between each of the layers 48 and 48 and an interface A between the N- and P-type well regions 41 and 42.
A P.sup.+ -type source diffusion layer 49 having the same potential as that of the N-type well region 41 is formed in that portion of the surface of the N-type well region 41 which corresponds to a common source region between the gate polysilicon electrodes 47a and 47b. The layer 49 is drawn toward the interface A between the regions 41 and 42 and located at a fixed distance B.sub.2 (which is shorter than B.sub.1) from the interface A.
An N.sup.+ -type substrate diffusion layer 50 is formed selectively in part of the N-type well region 41 as one different from the source diffusion layer 49.
Drain contacts 51 and 51 are connected to their respective drain diffusion layers 48 and 48 through the gate insulation film 46. A source contact 52 is connected to the source diffusion layer 49 through the gate insulation film 46, and a substrate contact 54 is connected to the substrate diffusion layer 50 through an insulation film 53.
In the active region 45 of the N-channel MOS transistor, N.sup.+ -type drain diffusion layers 55 and 55 whose potential differs from that of the P-type well region 42 are formed in those portions of the surface of the P-type well region 42 which correspond to drain regions outside the gate polysilicon electrodes 47a and 47b.
An N.sup.+ -type source diffusion layer 56 having the same potential as that of the P-type well region 42 is formed in that portion of the surface of the P-type well region 42 which corresponds to a common source region between the gate polysilicon electrodes 47a and 47b.
A P.sup.+ -type substrate diffusion layer 57 is formed selectively in part of the P-type well region 42 as one different from the source diffusion layer 56.
Drain contacts 58 and 58 are connected to their respective drain diffusion layers 55 and 55 through the gate insulation film 46. A source contact 59 is connected to the source diffusion layer 56 through the gate insulation film 46, and a substrate contact 61 is connected to the substrate diffusion layer 57 through an insulation film 60.